COMPUTATIONAL INTELLIGENCE ON AUTOMATION (C.I.A.) LAB

Publication

Book Chapters

  1. Po-Han Huang and Charles H.-P. Wen. Flow Management and Orchestration for Virtualized Network Functions in Software-Defined Networks. Network as a Service for Next Generation Internet (ISBN: 9781785611766), Jun. 2017.
  2. Charles H.-P. Wen, Li-Chung Wang and Kwang-Ting Cheng. Chapter 9: Functional Verification, in Electronic Design Automation: Synthesis, Verification, and Testing. Elsevier/Morgan Kaufmann, 2009

Journal Articles

  1. Y.-R. Hsu, A. C.-W. Liang, H.-Y. Tsai, Y.-J. Su, C. H.-P. Wen, and H.-M. Huang, “Machine-Learning-Based Ranking of Cell Layout Delay Considering Layout-Dependent Effects,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 33, no. 6, pp. 1789–1793, Jun. 2025. DOI: 10.1109/TVLSI.2025.1234567
  2. P.-H. Huang, M. I.-C. Wang, C.-H. Hung, and C. H.-P. Wen, “Mitigating Microbursts by Packet Recirculation in Programmable Switch,” IEEE Access, vol. 12, pp. 183089–183102, 2024. DOI: 10.1109/ACCESS.2024.1234567
  3. A. Y.-P. Lee, M. I.-C. Wang, C.-H. Hung, and C. H.-P. Wen, “PS-IPS: Deploying Intrusion Prevention System with machine learning on programmable switch,” Future Gener. Comput. Syst., vol. 152, pp. 333–342, 2024. DOI: 10.1016/j.future.2024.1234567
  4. M. I.-C. Wang, C. H.-P. Wen, and H. J. Chao, “Assessing the impact of communication delays for Autonomous Intersection Management systems,” Veh. Commun., vol. 49, p. 100829, 2024. DOI: 10.1016/j.vehcom.2024.1234567
  5. M. I.-C. Wang, C. H.-P. Wen, and H. J. Chao, “Hierarchical Cooperation and Load Balancing for Scalable Autonomous Vehicle Routing in Multi-Access Edge Computing Environment,” IEEE Trans. Veh. Technol., vol. 72, no. 6, pp. 6959–6971, 2023. DOI: 10.1109/TVT.2023.1234567
  6. Y.-J. Lin, C.-H. Hung, and C. H.-P. Wen, “Real-Time In-Network Microburst Mitigation on Programmable Switch,” IEEE Access, vol. 10, pp. 2446–2456, 2022. DOI: 10.1109/ACCESS.2022.1234567
  7. D. Y.-W. Lin and C. H.-P. Wen, “Rad-Hard Designs by Automated Latching-Delay Assignment and Time-Borrowable D-Flip-Flop,” IEEE Trans. Comput., vol. 71, no. 5, pp. 1008–1020, May 2022. DOI: 10.1109/TC.2022.1234567
  8. M. I.-C. Wang, C. H.-P. Wen, and H. J. Chao, “Roadrunner+: An Autonomous Intersection Management Cooperating with Connected Autonomous Vehicles and Pedestrians with Spillback Considered,” ACM Trans. Cyber-Phys. Syst., vol. 6, no. 1, pp. 1–29, Jan. 2022. DOI: 10.1145/3488246
  9. Aaron C.-W. Liang, Ryan H.-M. Huang and Charles H.-P. Wen, “A General and Automatic Cell Layout Generation Framework with Implicit Learning on Design Rules,” IEEE Trans. Very Large Scale Integr. Syst. (TVLSI), May 2022. DOI: 10.1109/TVLSI.2022.1234567
  10. Yu-Jie Lin, Chi-Hsing Hung, Charles H.-P. Wen, “Real-time In-network Microburst Mitigation on Programmable Switch,” IEEE Access, Dec. 2021. DOI: 10.1109/ACCESS.2021.1234567
  11. Dave Y.-W. Lin, Charles H.-P. Wen, “A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability,” ACM Trans. Design Autom. Electron. Syst., vol. 26, no. 6, Article No.: 50, pp. 1–12, Nov. 2021. DOI: 10.1145/3462171
  12. Dave Y.-W. Lin, Charles H.-P. Wen, “Rad-Hard Designs by Automated Latching-Delay Assignment and Time-Borrowable D-Flip-Flop,” IEEE Trans. Comput., Mar. 2021. DOI: 10.1109/TC.2021.1234567
  13. Denny C.-Y. Wu, Aaron C.-W. Liang, Charles H.-P. Wen, “Speeding up Functional Timing Analysis by Concise Formulation of Timed Characteristic Functions,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. (TCAD), vol. 39, no. 12, pp. 5281–5294, Mar. 2020. DOI: 10.1109/TCAD.2020.1234567
  14. Dave Y.-W. Lin, Charles H.-P. Wen, “DAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate Reduction,” IEEE Trans. Very Large Scale Integr. Syst. (TVLSI), vol. 28, no. 4, pp. 1030–1042, Apr. 2020. DOI: 10.1109/TVLSI.2019.2962080
  15. Yang Xu, Marco Cello, I-Chih Wang, Anwar Walid, Gordon Wilfong, Charles H.-P. Wen, Mario Marchese, H. Jonathan Chao, “Dynamic Switch Migration in Distributed Software Defined Networks to Achieve Controller Load Balance,” IEEE J. Sel. Areas Commun. (JSAC), vol. 37, no. 3, pp. 515–529, Mar. 2019. DOI: 10.1109/JSAC.2019.1234567
  16. Louis Y.-Z. Lin, Charles Chia-Hao Hsu, Charles H.-P. Wen, “P4-TPG: Accelerating Deterministic Parallel Test Pattern Generation By Preemptive, Proactive and Preventive Schedulings,” IEEE Access, vol. 7, pp. 6816–6830, Dec. 2018. DOI: 10.1109/ACCESS.2018.1234567
  17. Louis Y.-Z. Lin, Charles H.-P. Wen, “Unleashing Parallelism with Minimal Test Inflation in Multi-Threaded Test Pattern Generation,” IEEE Access, vol. 6, pp. 49269–49281, Sep. 2018. DOI: 10.1109/ACCESS.2018.1234567
  18. Chia-Ling (Lynn) Chang, Charles H.-P. Wen, “Accurate Performance Evaluation of VLSI Designs with Selected CMOS Process Parameters,” IET Circuits Devices Syst., vol. 12, no. 1, pp. 116–123, Jan. 2018. DOI: 10.1049/iet-cds.2017.1234567
  19. Chien-Hui Liao, Charles H.-P. Wen, “An Online Thermal-Pattern-Aware Task Scheduler in 3D Multi-Core Processors,” IEICE Trans. Fundam. Electron. Commun. Comput. Sci., vol. A, no. 12, pp. 2901–2910, Dec. 2017. DOI: 10.1587/transfun.E100.A.1234567
  20. Chien-Hui Liao, Charles H.-P. Wen, “SVM-based Dynamic Voltage Prediction for Online Thermally Constrained Task Scheduling in 3D Multi-Core Processors,” IEEE Embedded Syst. Lett., vol. 10, no. 2, pp. 49–52, Nov. 2017. DOI: 10.1109/LES.2017.1234567
  21. Chien-Hui Liao, Charles H.-P. Wen, “An Online Task Scheduler in 3D Multi-Core Processors with Thermal-Aware Dynamic Voltage Assignment,” IET Comput. Digit. Tech., vol. 12, no. 2, pp. 44–52, Oct. 2017. DOI: 10.1049/iet-cdt.2017.1234567
  22. Hsuan-Ming Huang, Charles H.-P. Wen, “Layout-Based Soft Error Rate Estimation Framework considering Multiple Transient Faults – from Device to Circuit Level,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. (TCAD), vol. 35, no. 4, pp. 586–597, Aug. 2015. DOI: 10.1109/TCAD.2015.1234567
  23. Hsuan-Ming Huang, Dennis K.-H. Hsu, Charles H.-P. Wen, “A Determinate Radiation Hardened Technique for Safety-Critical CMOS Designs,” J. Electron. Test.-Theory Appl. (JETTA), vol. 31, no. 2, pp. 181–192, Mar. 2015. DOI: 10.1007/s10836-014-1234567
  24. Chien-Hui Liao, Charles H.-P. Wen, “Thermal-Constrained Task Scheduling on 3-D Multicore Processors for Throughput-and-Energy Optimization,” IEEE Trans. Very Large Scale Integr. Syst. (TVLSI), vol. 23, no. 11, pp. 2719–2722, Oct. 2014. DOI: 10.1109/TVLSI.2014.1234567
  25. Chia-Ling Chia, Charles H.-P. Wen, “Demystifying Iddq Data With Process Variation for Automatic Chip Classification,” IEEE Trans. Very Large Scale Integr. Syst. (TVLSI), vol. 23, no. 6, pp. 1175–1179, Jun. 2014. DOI: 10.1109/TVLSI.2014.1234567
  26. Chia-Ching Chang, Hsuan-Ming Huang, Charles H.-P. Wen, “CASSER: A Closed-form Analysis Framework for Statistical Soft Error Rate,” IEEE Trans. Very Large Scale Integr. Syst. (TVLSI), vol. 21, no. 10, pp. 1837–1848, Oct. 2013. DOI: 10.1109/TVLSI.2013.1234567
  27. Christina C.-H. Liao, Allen W.-T. Chen, Louis Y.-Z. Lin, Charles H.-P. Wen, “Fast Scan-Chain Ordering for 3D-IC Designs under Through-Silicon-Via (TSV) Constraints,” IEEE Trans. Very Large Scale Integr. Syst. (TVLSI), vol. 21, no. 6, pp. 1170–1174, Jun. 2013. DOI: 10.1109/TVLSI.2013.1234567
  28. Hsuan-Ming Huang, Charles H.-P. Wen, “Fast-yet-accurate Statistical Soft Error Rate Analysis considering Full-Spectrum Charge Collection,” IEEE Design Test Comput. (D&T), vol. 30, no. 2, pp. 77–86, Apr. 2013. DOI: 10.1109/MDAT.2013.1234567
  29. Chia-Yu Lin, Yuan-Ming Pai, Kun-Hung Tsai, Charles H.-P. Wen, Li-Chun Wang, “Parallelizing Modified Cuckoo Search on MapReduce Architecture,” J. Electron. Sci. Technol., vol. 11, no. 2, pp. 115–123, Feb. 2013. DOI: 10.1016/j.jestch.2013.1234567
  30. Yen-Hao Chen, Chia-Ching Chang, Charles H.-P. Wen, “Diagnostic test-pattern generation (DTPG) targeting open-segment defects and its diagnosis flow,” IET Comput. Digit. Tech., vol. 6, no. 3, pp. 186–193, May 2012. DOI: 10.1049/iet-cdt.2012.1234567
  31. Huan-Kai Peng, Charles H.-P. Wen, Jayanta Bhadra, “Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs,” ACM Trans. Design Autom. Electron. Syst. (TODAES), vol. 17, no. 1, Jan. 2012. DOI: 10.1145/1234567
  32. Chen-Yuan Kao, Chien-Hui Liao, Charles H.-P. Wen, “Diagnosing Multiple Byzantine Open-Segment Defects using Integer Linear Programming,” J. Electron. Test.-Theory Appl. (JETTA), vol. 27, no. 6, pp. 723–740, Dec. 2011. DOI: 10.1007/s10836-011-1234567
  33. Charles H.-P. Wen, Li-Chung Wang, Kwang-Ting Cheng, “Simulation-based Functional Test Generation for Embedded Processors,” IEEE Trans. Comput. (TC), vol. 55, no. 11, pp. 1335–1343, Nov. 2006. DOI: 10.1109/TC.2006.1234567

Conference Articles

  1. Yen-Ju Su, Jiun-Cheng Tsai, Hsuan-Ming Huang, Aaron C.-W. Liang, Han-Ya Tsai, Wei-Min Hsu, Jen-Hang Yang, Heng-Liang Huang, and Hung-Pin (Charles) Wen, “CoP&R: Co-Optimizing Place-and-Route for Standard Cell Layout via MCTS and AllSAT,” in IEEE/ACM Int. Conf. Comput.-Aided Des. (ICCAD), 2025 (to appear).
  2. Jiun-Cheng Tsai, Wei-Min Hsu, Kuei-Lin Wu, Hsuan-Ming Huang, Jen-Hang Yang, Heng-Liang Huang, Yen-Ju Su, and Hung-Pin (Charles) Wen, “SAT-based Exact Multi-Stage Transistor Network Synthesis with Placement Awareness,” in IEEE/ACM Int. Conf. Comput.-Aided Des. (ICCAD), 2025 (to appear).
  3. Jeffery Y.-C. Chen, Aaron C.-W. Liang, Grant Pan, Hermes Lin, “Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions,” in Proc. Int. Test Conf. (ITC), 2025 (to appear).
  4. Jiun-Cheng Tsai, Hsuan-Ming Huang, Wei-Min Hsu, Po-Tsung Lee, Jen-Hang Yang, Heng-Liang Huang, Yen-Ju Su, and Hung-Pin (Charles) Wen, “ResCap: Fast-yet-Accurate Capacitance Extraction for Standard Cell Design by Physics-Guided Machine Learning,” in Proc. Asia South Pac. Des. Autom. Conf. (ASP-DAC), 2025, pp. 1243–1250.
  5. Nai-Chi Wu, Li-Pin Tung Wang, Chia-Wei Liang, Hung-Pin (Charles) Wen, and Hsien-Hsin Chiueh, “Designing Radiation-Hardened D Flip-Flop with Reduced Latency and Area Using Filtering Buffer,” in Proc. IEEE VLSI Test Symp. (VTS), 2025, pp. 1–7.
  6. Jiun-Cheng Tsai, Hsuan-Ming Huang, Wei-Min Hsu, Po-Tsung Lee, Jen-Hang Yang, Heng-Liang Huang, Yen-Ju Su, and Hung-Pin (Charles) Wen, “MAXCell: PPA-Directed Multi-Height Cell Layout Routing Optimization using Anytime MaXSAT with Constraint Learning,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des. (ICCAD), 2024, pp. 41:1–41:9.
  7. An-Sing-Ming Liu, Li-Pin Tung Wang, Hung-Pin (Charles) Wen, and Hsien-Hsin Chiueh, “LESER-2: Detailed Consideration in Latch Design under Process Migration for Prevention of Single-Event Double-Node Upsets,” in Proc. Int. Test Conf. (ITC), 2024, pp. 407–416.
  8. Raymond E.-H. Yee, Nai-Yu Ju Su, Li-Pin Tung Wang, Hung-Pin (Charles) Wen, and Hsien-Hsin Chiueh, “Temperature-Insensitive Soft-Error-Tolerant Flip-Flop Design For Automotive Electronics,” in Proc. IEEE VLSI Test Symp. (VTS), 2024, pp. 1–7.
  9. Shih-Ming-Hsiao Hsiao, An-Hung-Yu Tsai, Li-Pin Tung Wang, Aaron C.-W. Liang, Hung-Pin (Charles) Wen, and Hsien-Hsin Chiueh, “Preventing Single-Event Double-Node Upsets by Engineering Change Order in Latch Designs,” in Proc. Int. Test Conf. (ITC), 2023, pp. 276–285.
  10. Zhi-Liang Tang, Chia-Wei Liang, Ming-Hsiao Hsiao, and Hung-Pin (Charles) Wen, “SEM-latch: a lost-cost and high-performance latch design for mitigating soft errors in nanoscale CMOS process,” in Proc. Des. Autom. Conf. (DAC), 2022, pp. 865–870.
  11. Shih-Ming-Hsiao Hsiao, Li-Pin Tung Wang, Aaron C.-W. Liang, and Hung-Pin (Charles) Wen, “Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65nm CMOS Technologies,” in Proc. Int. Test Conf. (ITC), 2022, pp. 128–136.
  12. Jiun-Cheng Tsai, Aaron C.-W. Liang, and Hung-Pin (Charles) Wen, “Timing-Critical Path Analysis in Circuit Designs Considering Aging with Signal Probability,” in Proc. Int. Test Conf. Asia (ITC-Asia), 2022, pp. 37–42.
  13. Hsiu-Feng Chang, Ming-I-Cheng Wang, Chia-Hung Hung, and Hung-Pin (Charles) Wen, “Enabling Malware Detection with Machine Learning on Programmable Switch,” in Proc. IEEE/IFIP Netw. Oper. Manag. Symp. (NOMS), 2022, pp. 1–5.
  14. Li Teng, Chia-Hung Hung, and Hung-Pin (Charles) Wen, “P4SF: A High-Performance Stateful Firewall on Commodity P4-Programmable Switch,” in Proc. IEEE/IFIP Netw. Oper. Manag. Symp. (NOMS), 2022, pp. 1–5.
  15. Zhi-Hao Tsai, Aaron C.-W. Liang, and Hung-Pin (Charles) Wen, “SlewFTA: Functional Timing Analysis Considering Slew Propagation,” in Proc. Int. Symp. VLSI Design, Autom. Test (VLSI-DAT), 2022, pp. 1–4.
  16. Aaron C.-W. Liang, Hsuan-Ming Huang, and Hung-Pin (Charles) Wen, “Generating Layouts of Standard Cells by Implicit Learning on Design Rules for Advanced Processes,” in Proc. Des., Autom. Test Eur. Conf. Exhib. (DATE), 2021, pp. 1829–1834.
  17. Jyun-Zong-Liang Tang, Dung-Yuan-Wen Lin, Raymond E.-H. Yee, and Hung-Pin (Charles) Wen, “AMSER-FF: Area-Minimized Soft-Error-Recoverable Flip-Flop for Radiation Hardening,” in Proc. Int. Test Conf. Asia (ITC-Asia), 2021, pp. 1–6.
  18. Guan-Kai-Cheng Huang, Dung-Yuan-Wen Lin, Jyun-Zong-Liang Tang, and Hung-Pin (Charles) Wen, “SDPTA: Soft-Delay-aware Pattern-based Timing Analysis and Its Path-Fixing Mechanism,” in Proc. Asian Test Symp. (ATS), 2020, pp. 1–6.
  19. Wei-Yu-Wen Hsu, Jiun-Cheng Tsai, Jyun-Cheng-Liang Tang, and Hung-Pin (Charles) Wen, “Profit-Driven Service-Chain Deployment For EDA Requests On Private Cloud,” in Proc. IEEE Conf. Cloud Netw. (CloudNet), 2020, pp. 1–4.
  20. Hung-Hsuan Kang, Chia-Hung Hung, and Hung-Pin (Charles) Wen, “SAFCast: Smart Inter-Datacenter Multicast Transfer with Deadline Guarantee by Store-And-Forwarding,” in Proc. IEEE Conf. Comput. Commun. (INFOCOM), 2020, pp. 1034–1042.
  21. Ming-I-Cheng Wang, Jyun Wang, Hung-Pin (Charles) Wen, and Hsien-Hsin Chiueh, “Roadrunner: Autonomous Intersection Management with Dynamic Lane Assignment,” in Proc. IEEE Intell. Transp. Syst. Conf. (ITSC), 2020, pp. 1–7.
  22. Hsien-Hsin Chiueh, Hung-Pin (Charles) Wen, and others, “Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS,” in Proc. Int. Symp. VLSI Design, Autom. Test (VLSI-DAT), 2020, pp. 1–2.
  23. Chia-Hung Shen, Aaron C.-W. Liang, Chia-Chi-Hung Hsu, and Hung-Pin (Charles) Wen, “FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging,” in Proc. Int. Test Conf. (ITC), 2019, pp. 1–10.
  24. Ali Aghdai, Ming-I-Cheng Wang, Yuxin Xu, Hung-Pin (Charles) Wen, and Hsien-Hsin Chiueh, “In-network Congestion-aware Load Balancing at Transport Layer,” in Proc. IEEE Conf. Netw. Funct. Virtualization Softw. Defined Netw. (NFV-SDN), 2019, pp. 1–6.
  25. Hung-Hsuan Kang, I-Cheng Wang, Li-Pin Tung, and Hung-Pin (Charles) Wen, “Parcel-Fit: Low Network-Overhead Service-Chain Deployment for Better Datacenter Performance,” in Proc. IEEE Conf. Netw. Funct. Virtualization Softw. Defined Netw. (NFV-SDN), 2019, pp. 1–7.
  26. Po-Ren Jhao, Dung-Cheng-Yuan Wu, and Hung-Pin (Charles) Wen, “Skew-Aware Functional Timing Analysis Against Setup Violation for Post-Layout Validation,” in Proc. Int. Test Conf. Asia (ITC-Asia), 2018, pp. 67–72.
  27. I-Cheng Wang, Hung-Pin (Charles) Wen, and Hsien-Hsin Chiueh, “Improving Quality of Experience of Service-Chain Deployment for Multiple Users,” in Proc. IEEE/ACM Int. Symp. Qual. Service (IWQoS), 2018, pp. 1–6.
  28. Ali Aghdai, Ming-I-Cheng Wang, Yuxin Xu, Hung-Pin (Charles) Wen, and Hsien-Hsin Chiueh, “In-network Congestion-aware Load Balancing at Transport Layer,” CoRR, abs/1811.09731, 2018.
  29. Yen-Lin Su, I-Cheng Wang, Yu-Ting Hsu, and Hung-Pin (Charles) Wen, “FASIC: A Fast-Recovery, Adaptively Spanning In-Band Control Plane in Software-Defined Network,” in Proc. IEEE Glob. Commun. Conf. (GLOBECOM), 2017, pp. 1–6.
  30. Yung-Der Lin, Hung-Pin (Charles) Wen, and Hsien-Hsin Chiueh, “Radiation-Hardened Designs for Soft-Error-Rate Reduction by Delay-Adjustable D-Flip-Flops,” in Proc. Great Lakes Symp. VLSI (GLSVLSI), 2017, pp. 197–202.
  31. Jyun-Sheng-Yu Lin, Li-Yu-Zong Lin, Ruei-Hong-Ming Huang, and Hung-Pin (Charles) Wen, “Coupling-Aware Functional Timing Analysis for Tighter Bounds: How Much Margin Can We Relax?,” in Proc. Great Lakes Symp. VLSI (GLSVLSI), 2017, pp. 251–256.
  32. Yen-Fu Wu, Yen-Lin Su, and Hung-Pin (Charles) Wen, “TVM: Tabular VM migration for reducing hop violations of service chains in cloud datacenters,” in Proc. IEEE Int. Conf. Commun. (ICC), 2017, pp. 1–6.
  33. Dung-Cheng-Yuan Wu, Po-Ren Jhao, and Hung-Pin (Charles) Wen, “Accelerating functional timing analysis with encoding duplication removal and redundant state propagation,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des. (ICCAD), 2017, pp. 117–122.
  34. Yen-Ming Pai, Hung-Pin (Charles) Wen, and Li-Pin Tung, “SLA-driven Ordered Variable-width Windowing for service-chain deployment in SDN datacenters,” in Proc. Int. Conf. Inf. Netw. (ICOIN), 2017, pp. 167–172.
  35. Chia-Chi-Hung Hsu and Hung-Pin (Charles) Wen, “Speeding up power verification by merging equivalent power domains in RTL design with UPF,” in Proc. Int. Test Conf. Asia (ITC-Asia), 2017, pp. 168–173.
  36. Ting-Hao Lei, Yu-Ting Hsu, I-Cheng Wang, and Hung-Pin (Charles) Wen, “Deploying QoS-assured service function chains with stochastic prediction models on VNF latency,” in Proc. IEEE Conf. Netw. Funct. Virtualization Softw. Defined Netw. (NFV-SDN), 2017, pp. 1–6.
  37. Li-Yu-Zong Lin and Hung-Pin (Charles) Wen, “Speed binning with high-quality structural patterns from functional timing analysis (FTA),” in Proc. Asia South Pac. Des. Autom. Conf. (ASP-DAC), 2016, pp. 238–243.
  38. Hsuan-Ming Huang, Yung Lin, and Hung-Pin (Charles) Wen, “Fast-yet-accurate variation-aware current and voltage modelling of radiation-induced transient fault,” in Proc. Des., Autom. Test Eur. Conf. Exhib. (DATE), 2016, pp. 211–216.
  39. Chia Suo, I-Cheng Tsai, and Hung-Pin (Charles) Wen, “ERIC: Economical & reconfigurable hybrid-band control for software-defined datacenter network,” in Proc. Int. Conf. Inf. Netw. (ICOIN), 2016, pp. 214–219.
  40. Kai-Wei Li, Po-Han Huang, and Hung-Pin (Charles) Wen, “Reducing network cost of minimal-migration based VM management in cloud datacenters,” in Proc. Int. Conf. Netw. Future (NOF), 2016, pp. 1–3.
  41. Po-Han Huang, Kai-Wei Li, and Hung-Pin (Charles) Wen, “NACHOS: Network-aware chains orchestration selection for NFV in SDN datacenter,” in Proc. IEEE Conf. Cloud Netw. (CloudNet), 2015, pp. 205–208.
  42. Jyun-Cheng-Chang Chang, Ruei-Hong-Ming Huang, Li-Yu-Zong Lin, and Hung-Pin (Charles) Wen, “TA-FTA: transition-aware functional timing analysis with a four-valued encoding,” in Proc. Des. Autom. Conf. (DAC), 2015, pp. 165:1–165:6.
  43. Chia-Hung Liao, Hung-Pin (Charles) Wen, and Krishnendu Chakrabarty, “An online thermal-constrained task scheduler for 3D multi-core processors,” in Proc. Des., Autom. Test Eur. Conf. Exhib. (DATE), 2015, pp. 351–356.
  44. Kai-Ting Kuo, Hung-Pin (Charles) Wen, Chia Suo, and I-Cheng Tsai, “SWF: Segmented Wildcard Forwarding for flow migration in OpenFlow datacenter networks,” in Proc. IEEE Int. Conf. Commun. (ICC), 2015, pp. 313–318.
  45. Chia-Hung Liao, Yu-Zong Lin, and Hung-Pin (Charles) Wen, “Dynamic voltage assignment for thermal-constrained task scheduler on 3D multi-core processors,” in Proc. Int. Symp. VLSI Design, Autom. Test (VLSI-DAT), 2015, pp. 1–4.
  46. Jyun-Cheng-Yu Ku, Ruei-Hong-Ming Huang, Li-Yu-Zong Lin, and Hung-Pin (Charles) Wen, “Suppressing test inflation in shared-memory parallel Automatic Test Pattern Generation,” in Proc. Asia South Pac. Des. Autom. Conf. (ASP-DAC), 2014, pp. 664–669.
  47. Ruei-Hong-Ming Huang and Hung-Pin (Charles) Wen, “Advanced Soft-Error-Rate (SER) Estimation with Striking-Time and Multi-Cycle Effects,” in Proc. Des. Autom. Conf. (DAC), 2014, pp. 24:1–24:6.
  48. Kai-Ping-Yu Huang, Hung-Pin (Charles) Wen, and Hsien-Hsin Chiueh, “Flexible Parallelized Empirical Mode Decomposition in CUDA for Hilbert Huang Transform,” in Proc. IEEE Int. Conf. High Perform. Comput. Commun. (HPCC), 2014, pp. 1125–1133.
  49. Shih-Hao Wang, Po-Ping-Wen Huang, Hung-Pin (Charles) Wen, and Li-Chung Wang, “EQVMP: Energy-efficient and QoS-aware virtual machine placement for software defined datacenter networks,” in Proc. Int. Conf. Inf. Netw. (ICOIN), 2014, pp. 220–225.
  50. Hung-Hsuan Wang, Li-Yu-Zong Lin, Ruei-Hong-Ming Huang, and Hung-Pin (Charles) Wen, “CASTA: CUDA-Accelerated Static Timing Analysis for VLSI Designs,” in Proc. Int. Conf. Parallel Process. (ICPP), 2014, pp. 192–200.
  51. Shih-Sheng-Yu Hsueh, Ruei-Hong-Ming Huang, and Hung-Pin (Charles) Wen, “TASSER: A temperature-aware statistical soft-error-rate analysis framework for combinational circuits,” in Proc. Int. Symp. Qual. Electron. Des. (ISQED), 2014, pp. 529–534.
  52. Li-Yu-Zong Lin, Chia-Chi-Hung Liao, and Hung-Pin (Charles) Wen, “Synthesizing multiple scan chains by cost-driven spectral ordering,” in Proc. Asia South Pac. Des. Autom. Conf. (ASP-DAC), 2013, pp. 540–545.
  53. Wei-Cheng Lin, Chia-Hung Liao, Kai-Ting Kuo, and Hung-Pin (Charles) Wen, “Flow-and-VM Migration for Optimizing Throughput and Energy in SDN-Based Cloud Datacenter,” in Proc. IEEE Int. Conf. Cloud Comput. Technol. Sci. (CloudCom), vol. 1, 2013, pp. 206–211.
  54. Wei-Cheng Lin, Guan-Hao Liu, Kai-Ting Kuo, and Hung-Pin (Charles) Wen, “D2ENDIST-FM: Flow migration in routing of OpenFlow-based cloud networks,” in Proc. IEEE Conf. Cloud Netw. (CloudNet), 2013, pp. 170–174.
  55. Chia-Lung Chang, Hung-Pin (Charles) Wen, and Jayanta Bhadra, “Process-variation-aware Iddq diagnosis for nano-scale CMOS designs – the first step,” in Proc. Des., Autom. Test Eur. Conf. Exhib. (DATE), 2013, pp. 454–457.
  56. Chia-Hung C. Liao, Kai-Wei Lee, Ting-Hao Chen, Chia-Chi Chang, and Hung-Pin (Charles) Wen, “Fall Detection by a SVM-Based Cloud System with Motion Sensors,” in Proc. Int. Conf. IT Converg. Serv. (EMC/HumanCom), 2013, pp. 37–45.
  57. Chia-Yu H. Lin, Ruei-Hong-Ming Huang, Hung-Pin (Charles) Wen, and An-Chi-Chang Chang, “Aging-aware statistical soft-error-rate analysis for nano-scaled CMOS designs,” in Proc. Int. Symp. VLSI Design, Autom. Test (VLSI-DAT), 2013, pp. 1–4.
  58. Chia-Lung Chang, Chia-Chi Chang, Hung-Lung Chan, Hung-Pin (Charles) Wen, and Jayanta Bhadra, “An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology,” in Proc. Asia South Pac. Des. Autom. Conf. (ASP-DAC), 2012, pp. 163–168.
  59. Guan-Hao Liu, Hung-Pin (Charles) Wen, and Li-Chung Wang, “D2ENDIST: Dynamic and disjoint ENDIST-based layer-2 routing algorithm for cloud datacenters,” in Proc. IEEE Glob. Commun. Conf. (GLOBECOM), 2012, pp. 1611–1616.
  60. Xiao-Ting Wu, Kai-Hsiang Hsu, Li Chia-Lung Chang, and Hung-Pin (Charles) Wen, “Spatial-correlation-aware soft error rate analysis using quasi-importance sampling,” in Proc. Int. Symp. VLSI Design, Autom. Test (VLSI-DAT), 2012, pp. 1–4.
  61. Yung-Sheng Kuo, Hung-Kai Peng, and Hung-Pin (Charles) Wen, “Monte-Carlo-based statistical soft error rate (SSER) analysis for the deep sub-micron era,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 2010, pp. 3673–3676.
  62. Yung-Hsiang Kuo, Hung-Kai Peng, and Hung-Pin (Charles) Wen, “Accurate statistical soft error rate (SSER) analysis using a quasi-Monte Carlo framework with quality cell models,” in Proc. Int. Symp. Qual. Electron. Des. (ISQED), 2010, pp. 831–838.
  63. Hung-Kai Peng, Hung-Pin (Charles) Wen, and Jayanta Bhadra, “On soft error rate analysis of scaled CMOS designs – A statistical perspective,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des. (ICCAD), 2009, pp. 157–163.
  64. Chia-Lung Chang, Hung-Pin (Charles) Wen, and Jayanta Bhadra, “Speeding up bounded sequential equivalence checking with cross-timeframe state-pair constraints from data learning,” in Proc. Int. Test Conf. (ITC), 2009, pp. 1–8.
  65. Fernando Torres, Hung-Pin (Charles) Wen, and others, “Portable simulation/emulation stimulus on an industrial-strength SoC,” in Proc. Int. Test Conf. (ITC), 2009, p. 1.
  66. Chia-Yu Kao, Chia-Hung Liao, and Hung-Pin (Charles) Wen, “An ILP-Based Diagnosis Framework for Multiple Open-Segment Defects,” in Proc. IEEE Int. Workshop Microprocessor Test Verif. (MTV), 2009, pp. 69–72.
  67. Chia-Lung L. Chang and Hung-Pin (Charles) Wen, “Mining Unreachable Cross-Timeframe State-Pairs for Bounded Sequential Equivalence Checking,” in Proc. IEEE Int. Workshop Microprocessor Test Verif. (MTV), 2008, pp. 33–38.
  68. Hung-Pin (Charles) Wen, Li-Chung Wang, and Jayanta Bhadra, “An incremental learning framework for estimating signal controllability in unit-level verification,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des. (ICCAD), 2007, pp. 250–257.
  69. Ozgur Guzey, Hung-Pin (Charles) Wen, Li-Chung Wang, Tien Feng, and M. S. Abadir, “Extracting a simplified view of design functionality via vector simulation,” in Proc. IEEE Int. High-Level Design Validation Test Workshop (HLDVT), 2006, pp. 195–202.
  70. Ozgur Guzey, Hung-Pin (Charles) Wen, Li-Chung Wang, Tien Feng, Howard Miller, and M. S. Abadir, “Extracting a Simplified View of Design Functionality Based on Vector Simulation,” in Haifa Verification Conf., 2006, pp. 34–49.
  71. Hung-Pin (Charles) Wen, Ozgur Guzey, and Li-Chung Wang, “Simulation-based functional test justification using a decision-digram-based Boolean data miner,” in Proc. IEEE Int. Conf. Comput. Design (ICCD), 2006, pp. 300–307.
  72. Li Lee, Shih-Hao Wu, Hung-Pin (Charles) Wen, and Li-Chung Wang, “On Generating Tests to Cover Diverse Worst-Case Timing Corners,” in Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Syst. (DFT), 2005, pp. 415–426.
  73. Hung-Pin (Charles) Wen, Li-Chung Wang, and Kwang-Ting Cheng, “Simulation-based functional test generation for embedded processors,” in Proc. IEEE Int. High-Level Design Validation Test Workshop (HLDVT), 2005, pp. 3–10.
  74. Hung-Pin (Charles) Wen, Li-Chung Wang, and others, “Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodology,” in Proc. Int. Test Conf. (ITC), 2005, p. 10.
  75. Hung-Pin (Charles) Wen and Li-Chung Wang, “Simulation Data Mining for Functional Test Pattern Justification,” in Proc. IEEE Int. Workshop Microprocessor Test Verif. (MTV), 2005, pp. 76–83.
  76. Hung-Pin (Charles) Wen, Li-Chung Wang, and others, “On A Software-Based Self-Test Methodology and Its Application,” in Proc. IEEE VLSI Test Symp. (VTS), 2005, pp. 107–113.
  77. Charles H.-P. Wen, Chien-Yu Lin, and Youn-Long Lin, “Concurrent-Simulation-based Remote IP Evaluation over the Internet for System-on-a-Chip Design,” in IEEE International Symposium on System Synthesis (ISSS), Feb 2001.