Current Themes
- (聯發科AI產學 2023-2026) ChatDTCO: Chat-based Design and Technology Co-Optimization for Generating Design Recipe
The optimization of IC designs is of utmost importance to meet the ever-growing demands for high-performance and low-power applications. It is crucial to address the complexity introduced by the multitude of design decisions and their impact on PPA. To effectively tackle this design optimization challenge, there is a pressing need for a comprehensive Design Technology Co-Optimization (DTCO) framework.
- (ITRI產學合作 2023) 應用於衛星地面站並使用 CMOS 65nm製程的數位積體電路設計
本計畫與工研院合作,配合衛星地面站的波束成型(Beamforming)系統,視其需求設計一個序列周邊介面(Serial Peripheral Interface),實現中低速的資料流傳輸,透過此資料傳輸介面將資料提供給內部射頻積體電路,以利後續波束成型系統的控制。
- (聯發科AI產學 2022) AI-Guided PPA Optimization for Standard Cell Design on Beyond N5 Node
A novel AI-guided standard cell design (AGSCD) framework is proposed to deal with the PPA-optimization problem for standard cell designs.
- (科技部EDA專案 2020-2023) Test-for-Zero: Smart Test Methodology Towards Zero Failure RateFor AI-inside Automotive Chip 分項(二)
In this project, we are developing an aging- and radiation-aware framework which hardens designs by DAD-FF, and meanwhile a BIST circuit monitors its reliability and the performance simultaneously to provide robustness.
- (ITRI產學合作 2022) Raidation-Hardened Chip Design in 65-nm Process for Low-Earth Orbit Satellite 分項(二)
To achieve zero error rate, we are developing a radiation-hardened D-type flip-flop in 65-nm process for synthesizing registers and other storage components.
- (科技部個人計畫 2021) Hardening Designs by Soft-Error Recoverable D Fllip-Flops (SERDFFs) with an OPtimization Algorithm on Configurations (OPAC)
In this two-year proposal, we are developing a radiation-hardened design with minimal timing overhead, maximizing the design performance.
- (經濟部旗艦計畫 2019-2023) Industrial Value Creation Program for Academia-Innovation and Services for IoT and 5G using SDN/NFV Technologies 分項(B)
In this MOEA project “Industrial Value Creation Program for Academia-Innovation and Services for IoT and 5G using SDN/NFV Technologies,” the applicant serves as the sub-project leader of sub-project B-Technology Development for Programmable Switch, and is mainly responsible for sub-project planning and integration and the management for NCTU P4 Testbeds.
- (智邦/鈺登產學 2020-2023) Intelligent Networking by High-Speed Programmable Switch
With the combination of INT and IBN, the network can be intelligent, enabling various automated network failure analysis, network management, energy management, and performance optimization.
- (教育部深耕計畫 2019-2023) Higher Education Sprout Project Center for Open Intelligent Connectivity (OpInConnect) 分項(D)
In the MOE project “Higher Education Sprout Project Center for Open Intelligent Connectivity (OpInConnect)”, the applicant serves as the leader of sub-project C-technology development for programmable switch and is mainly responsible for sub-project planning and integration, including the construction and management of the NCTU P4/INT Testbed and the prototype of P4/INT based microburst flow monitoring system, including an academia and industry collaboration project with Edgecore Network to develop P4/INT applications like P4-based Stateful Firewall.
Past Themes (Closed Projects)
- Machine-Learning-based Failure Triage for Debugging RTL Designs
This project is sponsored by Synopsys. All previous works on failure triage only rely data mining to analyze failure traces. This project aims at developing a failure-triage framework for later debugging RTL designs by modern machine learning and trying to provide extended explanation on the result of failure clusters. In the proposed framework, features of failure traces are derived from the synthesized gate-level netlist and defined by the suspect (single stuck-at) faults by SAT solving. We proposed an autoencoder-based failure binning engine name FAE for debugging RTL designs more efficiently. Superior to prior works, FAE provides confidence ranks between bins and in a bin to clearly guide designers during debugging. Experimental results show that FAE can drive bins of higher purity under an acceptable number of bins than prior works, dropping only few less-informative failures. Evaluated by three common metrics for clustering, FAE also achieves averagely 13.1% improvement in purity, 25.0% improvement in NMI and 18.2% improvement in ARI, respectively.
- Layout-Based Soft Error Rate Estimation and Optimization considering Multiple Transient Faults
This study investigated the soft errors caused by particle strikes, such as high-energy neutrons, extending beyond the deep submicron era. Considering the structure of the layout and resulting nuclear reactions, multiple transient faults tend to be induced more frequently than single transient faults, due to the effects of technology scaling. This means that the soft error rates are beyond traditional netlist-based single transient fault analysis. This study proposes a layout-based soft error estimation framework, which takes into account multiple transient faults from the device level to the circuit level. This framework comprises two systems: generation and propagation. In the generation system, transient faults are modeled through nuclear reactions, charge collection, and voltage transformation at the device level. The propagation system abstracts these effects from the device level to the circuit level, taking into account three masking mechanisms associated with the propagation of transient faults. Upon observing the fundamental phenomena, various techniques including gate sizing, supply-voltage scaling, theshold-voltage scaling and etc. are investigated to optimize the soft error rate (SER) of the VLSI designs. Moreover, timing analysis is crucial for verifying whether a circuit design can operate without errors. Soft-delay effect (SDE), which is a kind of degraded soft error, will make system failed though the circuit has passed the typical timing analysis. Therefore, we propose a soft-delay-aware timing analysis which takes SDE into consideration. Additionally, a path-fixing mechanism is also proposed to fix up the violated paths automatically. Experimental results show that only 1.05% area budget is required averagely that all violated paths can be fixed up. In summary, SDPTA and the path-fixing mechanism are capable of reducing SDE to general circuits without other manual effort.
- SDN-enabled Cloud-based Wireless/Broadband Network
In the MOST project “SDN-enabled Cloud-based Wireless/Broadband Network”, the applicant serves as the sub-project leader of B.1 SDN-based mobile service network and is mainly responsible for sub-project planning and integration. The sub-project B.1 included an Academia and Industry Collaboration with Chunghwa Telecom Laboratories and helped them file two patent (SLA-driven Ordered Variable-width Windowing for Service-chain Deployment in SDN Datacenters and TVM: Tabular VM Migration for Reducing Hop Violations of Service Chains in Cloud Datacenters). Three SDN/NFV prototypes about mobile service chaining and mobile edge computing were delivered. They are (A) APIs of VM Migration for OpenStack, (B) a prototype of VM Placement for SDN-based Service Chaining using Sliding Windows Technologies and (C) a prototype of multi-site resource management for mobile edge computing.
- Knowledge Discovery and Mining of IDDQ Data for Nanoscale CMOS Designs
In this MOST project Knowledge Discovery and Mining of IDDQ Data for Nanoscale CMOS Designs, a new Iddq testing method is developed and won the best paper award of ASPDAC 2012. As the scale of silicon technology continues shrinking, Iddq values and associated fluctuations increase. In addition, increased design complexity makes defect-induced leakage currents difficult to differentiate from full-chip currents. Consequently, traditional Iddq methods result in more test escapes and yield loss. We propose a new test method, called sigma-Iddq to perform (A) Iddq analysis with process-parameter deduction and (B) the algorithm for automatic chip-classification called collective analysis without manually determining threshold values. Experimental results demonstrate that the proposed sigma-Iddq method can achieve higher classification accuracy than single threshold Iddq testing or delta-Iddq in a 45-nm technology. The overall classification accuracy of the collective analysis achieves averaged 99.28% and 99.70% on sigma-Iddq data from process-parameter deductions with average-case search and multilevel search, respectively, demonstrating that the influence of process variation and design scaling can be significantly reduced to enable a better identification of defective chips.
Recent Projects
- Title: Industrial Value Creation Program for Academia-Innovation and Services for IoT and 5G using SDN/NFV Technologies funded by Ministry of Economic Affairs (MOEA), Taiwan, Co-Principal Investigator (Co-PI) & Sub-Project Leader, $55,500,000, 2018/11/01~2019/10/31.
- Title: Intelligent Networking funded by Edgecore Networks Corporation, Co-Principal Investigator (Co-PI), $1,000,000, 2018/08/01~2019/07/31.
- Title: Higher Education Sprout Project Center for Open Intelligent Connectivity (OpInConnect) funded by Ministry of Education (MOE), Taiwan, Co-Principal Investigator (Co-PI) & Sub-Project Leader, $35,000,000, 2018/07/01~2019/06/30.
- Title: Machine-Learning-based Failure Triage for Debugging RTL Designs funded by Synopsys Inc., Principal Investigator (PI), $1,200,000, 2017/01/20~2018/01/19.
- Title: Layout-Based Soft Error Rate Estimation and Optimization considering Multiple Transient Faults funded by Ministry of Science and Technology (MOST), Taiwan, Principal Investigator (PI), $3,574,000, 2015/08/01~2018/07/31.
- Title: SDN-enabled Cloud-based Wireless/Broadband Network funded by Ministry of Science and Technology (MOST), Taiwan, Co-Principal Investigator (Co-PI) & Sub-Project Leader, $171,000,000, 2014/08/01~2017/07/31.
- Title: Knowledge Discovery and Mining of IDDQ Data for Nanoscale CMOS Designs funded by Ministry of Science and Technology (MOST), Taiwan, Principal Investigator (PI), $2,240,000, 2014/05/01~2016/04/30.